Memory cell array having ferroelectric capacitors, method of fabricating the same, and ferroelectric memory device

ABSTRACT

The present invention relates to: a memory cell array which is capable of decreasing the parasitic capacitance of signal electrodes and has ferroelectric layers making up ferroelectric capacitors and having a predetermined pattern; a method of fabricating the memory cell array, and a ferroelectric memory device. In the memory cell array, memory cells formed of ferroelectric capacitors are arranged in a matrix. The ferroelectric capacitors include first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and ferroelectric layers disposed linearly along either the first signal electrodes or the second signal electrodes. Alternatively, the ferroelectric layers may be disposed only in intersection areas of the first and second signal electrodes.

[0001] Japanese Patent Application No. 2000-251436, filed on Aug. 22,2000, is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

[0002] The present invention relates to a memory cell array havingferroelectric capacitors. More particularly, the present inventionrelates to a simple matrix memory cell array using only ferroelectriccapacitors instead of cell transistors, a method of fabricating thesame, and a ferroelectric memory device including the memory cell array.

BACKGROUND

[0003] A simple matrix memory cell array using only ferroelectriccapacitors instead of cell transistors has a very simple structure andenables a higher degree of integration. Therefore, development of such amemory cell array has been expected.

SUMMARY OF THE INVENTION

[0004] An objective of the present invention is to provide: a memorycell array which is capable of decreasing the parasitic capacitance ofsignal electrodes and has ferroelectric layers making up ferroelectriccapacitors and having a predetermined pattern; a method of fabricatingthe same; and a ferroelectric memory device including the memory cellarray of the present invention.

[0005] According to a first aspect of the present invention, there isprovided a first memory cell array having ferroelectric capacitors,wherein:

[0006] memory cells formed of ferroelectric capacitors are arranged in amatrix;

[0007] each of the ferroelectric capacitors includes a first signalelectrode, a second signal electrode disposed in a directionintersecting the first signal electrode, and a ferroelectric layerdisposed at least in an intersection area of the first and second signalelectrodes; and

[0008] the ferroelectric layer is disposed linearly along one of thefirst signal electrode and the second signal electrode.

[0009] Specifically, the memory cell array may have: (1) a structure inwhich the ferroelectric layer is selectively disposed over the firstsignal electrode; or (2) a structure in which the ferroelectric layer isselectively disposed under the second signal electrode.

[0010] In this memory cell array, since the ferroelectric layer isformed linearly along one of the first and second signal electrode, theparasitic capacitance of the other of the first and second signalelectrodes can be decreased.

[0011] According to a second aspect of the present invention, there isprovided a second memory cell array having ferroelectric capacitors,wherein:

[0012] memory cells formed of ferroelectric capacitors are arranged in amatrix;

[0013] each of the ferroelectric capacitors includes a first signalelectrode, a second signal electrode disposed in a directionintersecting the first signal electrode, and a ferroelectric layerdisposed at least in an intersection area of the first and second signalelectrodes; and

[0014] the ferroelectric layer is disposed only in the intersection areaof the first and second signal electrodes. In this memory cell array,since the ferroelectric layers making up the ferroelectric capacitorsare formed in the smallest region, the parasitic capacitance of thesignal electrodes can be further decreased.

[0015] In this memory cell array, since the ferroelectric layer formingthe ferroelectric capacitor has a minimum area, the parasiticcapacitance of the signal electrodes can be further reduced.

[0016] The above memory cell arrays have the following features.

[0017] (A) The ferroelectric capacitors may be disposed on a base; and adielectric layer may be provided between laminates each of whichincludes the first signal electrode and the ferroelectric layer so as tocover an exposed surface of the base. In this case, the dielectric layermay be formed of a material having a dielectric constant lower than adielectric constant of the ferroelectric layer. The parasiticcapacitance of the signal electrodes can be reduced effectively byproviding such dielectric layer.

[0018] (B) An undercoat layer having surface properties differing fromsurface properties of the base may be formed on the base. By providingsuch undercoat layer, at least either the signal electrode or theferroelectric layer can be formed selectively without etching. Theundercoat layer may be provided in an area in which the ferroelectriccapacitors are not formed; and a surface of the undercoat layer may havea low affinity for a material forming the ferroelectric capacitors, incomparison with a surface of the base. Alternatively, the undercoatlayer may be provided in an area in which the ferroelectric capacitorsare formed; and a surface of the undercoat layer may have a highaffinity for a material forming the ferroelectric capacitors, incomparison with a surface of the base.

[0019] According to a third aspect of the present invention, there isprovided a method of fabricating a memory cell array in which memorycells formed of ferroelectric capacitors are arranged in a matrix,comprising the steps of:

[0020] forming a first signal electrode with a predetermined pattern ona base;

[0021] selectively forming a ferroelectric layer on the first signalelectrode linearly along the first signal electrode; and

[0022] forming a second signal electrode in a direction intersecting thefirst signal electrode.

[0023] This fabrication method may further comprise the steps of:forming on the base a first region having surface properties which givepriority in deposition to a material of at least one of the first signalelectrode and the ferroelectric layer, and a second region havingsurface properties which give difficulty in deposition to the materialof at least one of the first signal electrode and the ferroelectriclayer in comparison with the first region; and providing the material ofat least one of the first signal electrode and the ferroelectric layerand selectively forming one of the first signal electrode and theferroelectric layer in the first region. The first and second regionsmay be defined on a surface of the base.

[0024] In this fabrication method, the surface of the base may beexposed in the first region; and in the second region may be formed anundercoat layer having surface properties having a low affinity formaterials of the first signal electrode and the ferroelectric layer incomparison with the exposed surface of the base in the first region.Alternatively, in this fabrication method, the surface of the base maybe exposed in the second region; and in the first region may be formedan undercoat layer having surface properties having a high affinity formaterials of the first signal electrode and the ferroelectric layer incomparison with the exposed surface of the base in the second region.

[0025] According to a fourth aspect of the present invention, there isprovided a method of fabricating a memory cell array in which memorycells formed of ferroelectric capacitors are arranged in a matrix,comprising the steps of:

[0026] forming a first signal electrode with a predetermined pattern ona base; and

[0027] forming a ferroelectric layer and a second signal electrode in adirection intersecting the first signal electrode, wherein theferroelectric layer is disposed linearly along the second signalelectrode.

[0028] In this fabrication method, the ferroelectric layer and thesecond signal electrode may be patterned by etching using the same mask.

[0029] According to a fifth aspect of the present invention, there isprovided a method of fabricating a memory cell array in which memorycells formed of ferroelectric capacitors are arranged in a matrix,comprising the steps of:

[0030] forming a first signal electrode with a predetermined pattern ona base;

[0031] forming a ferroelectric layer on the first signal electrodelinearly along the first signal electrode;

[0032] forming a second signal electrode in a direction intersecting thefirst signal electrode; and

[0033] patterning the ferroelectric layer to be disposed only in anintersection area of the first and second signal electrodes.

[0034] In this fabrication method, at least either the signal electrodeor ferroelectric layers may be provided by using the above-describedundercoat layer. The ferroelectric layers and the signal electrode maybe patterned by etching using the same mask.

[0035] In each of the above fabrication methods, the dielectric layermay be provided between laminates which include the signal electrode andthe ferroelectric layer so as to cover at least an exposed surface ofthe base.

[0036] According to a sixth aspect of the present invention, there isprovided a ferroelectric memory device comprising the memory cell arrayaccording to the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0037]FIG. 1 is a plan view schematically showing a memory cell arrayaccording to a first embodiment of the present invention.

[0038]FIG. 2 is a view showing a ferroelectric memory device accordingto the first embodiment of the present invention.

[0039]FIG. 3 is an enlarged plan view showing a portion of the memorycell array shown in FIG. 1.

[0040]FIG. 4 is a cross-sectional view along the line A-A shown in FIG.3.

[0041]FIG. 5 is a cross-sectional view schematically showing a step of amethod of fabricating a memory cell array according to the firstembodiment of the present invention.

[0042]FIG. 6 is a cross-sectional view schematically showing a step ofthe method of fabricating a memory cell array according to the firstembodiment of the present invention.

[0043]FIG. 7 is a plan view schematically showing a memory cell arrayaccording to a second embodiment of the present invention.

[0044]FIG. 8 is a cross-sectional view along the line B-B shown in FIG.7.

[0045]FIG. 9 is a cross-sectional view schematically showing a step of amethod of fabricating a memory cell array according to the secondembodiment of the present invention.

[0046]FIG. 10 is a cross-sectional view schematically showing a step ofthe method of fabricating a memory cell array according to the secondembodiment of the present invention.

[0047]FIG. 11 is a cross-sectional view schematically showing a step ofthe method of fabricating a memory cell array according to the secondembodiment of the present invention.

[0048]FIG. 12 is a cross-sectional view schematically showing a step ofthe method of fabricating a memory cell array according to the secondembodiment of the present invention.

[0049]FIG. 13 is a plan view schematically showing a memory cell arrayaccording to a third embodiment of the present invention.

[0050]FIG. 14 is a cross-sectional view along the line C-C shown in FIG.13.

[0051]FIG. 15 is a cross-sectional view along the line D1-D1 shown inFIG. 13.

[0052]FIG. 16 is a cross-sectional view along the line D2-D2 shown inFIG. 13.

[0053]FIG. 17 is a plan view schematically showing a step of a method offabricating a memory cell array according to the third embodiment of thepresent invention.

[0054]FIG. 18 is a cross-sectional view schematically showing a step ofthe method of fabricating a memory cell array according to the thirdembodiment of the present invention.

[0055]FIG. 19 is a cross-sectional view schematically showing a step ofthe method of fabricating a memory cell array according to the thirdembodiment of the present invention.

[0056]FIG. 20 is a cross-sectional view schematically showing a step ofthe method of fabricating a memory cell array according to the thirdembodiment of the present invention.

[0057]FIG. 21 is a cross-sectional view along the line E-E shown in FIG.17, which schematically shows a step of the method of fabricating amemory cell array according to the third embodiment of the presentinvention.

[0058]FIG. 22 is a plan view schematically showing a step of the methodof fabricating a memory cell array according to the third embodiment ofthe present invention.

[0059]FIG. 23 is a cross-sectional view along the line F1-F1 shown inFIG. 22, which schematically shows a step of the method of fabricating amemory cell array according to the third embodiment of the presentinvention.

[0060]FIG. 24 is a cross-sectional view along the line F2-F2 shown inFIG. 22, which schematically shows a step of the method of fabricating amemory cell array according to the third embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0061] First Embodiment

[0062] (Device)

[0063]FIG. 1 is a plan view schematically showing a memory cell arrayaccording to this embodiment. FIG. 2 is a view showing a ferroelectricmemory device according to this embodiment. FIG. 3 is an enlarged planview showing part of the memory cell array (portion indicated by symbol“A” in FIG. 1) shown in FIG. 1. FIG. 4 is a cross-sectional view alongthe line A-A shown in FIG. 3. In the plan views, numerals in parenthesesindicate layers under the uppermost layers.

[0064] A ferroelectric memory device 1000 includes a memory cell array100A in which memory cells 20 are arranged in a simple matrix, andvarious types of circuits for allowing information to be selectivelywritten into or read from the memory cell 20, such as a first drivercircuit 50 for selectively controlling first signal electrodes 12, asecond driver circuit 52 for selectively controlling second signalelectrodes 16, and a signal detecting circuit (not shown) such as asense amplifier, as shown in FIG. 2.

[0065] In the memory cell array 100A, the first signal electrodes (wordlines) 12 for selecting rows and the second signal electrodes (bitlines) 16 for selecting columns are arranged so as to intersect at rightangles. Specifically, the first signal electrodes 12 are arranged at aspecific pitch along the X direction. The second signal electrodes 16are arranged at a specific pitch along the Y direction which intersectthe X direction at right angles. The first signal electrodes may be thebit lines and the second signal electrodes may be the word lines,differing from this example.

[0066] In the memory cell array 100A, the first signal electrodes (lowerelectrodes) 12, ferroelectric layers 14 which make up ferroelectriccapacitors, and the second signal electrodes (upper electrodes) 16 arelayered on an insulating base 10, as shown in FIGS. 3 and 4. The firstsignal electrode 12, the ferroelectric layer 14, and the second signalelectrode 16 make up a ferroelectric capacitor 20. Specifically, memorycells consisting of the ferroelectric capacitors 20 are formed in eachintersection region between the first signal electrodes 12 and thesecond signal electrodes 16.

[0067] Dielectric layers 18 are formed between laminates consisting ofthe ferroelectric layer 14 and the second signal electrode 16 so as tocover exposed areas of the base 10 and the first signal electrodes 12.The dielectric layers 18 preferably have a dielectric constant lowerthan that of the ferroelectric layers 14. The parasitic capacitance ofthe second signal electrodes 16 can be decreased by allowing thedielectric layers 18 having a dielectric constant lower than that of theferroelectric layers 14 to be interposed between the laminatesconsisting of the ferroelectric layer 14 and the second signal electrode16. As a result, a read or write operation of the ferroelectric memorydevice 1000 can be performed at a higher speed.

[0068] In this embodiment, the ferroelectric layers 14 are formedlinearly along the second signal electrodes 16. The parasiticcapacitance of the first signal electrodes 12 can be decreased byforming the ferroelectric layers 14 linearly.

[0069] These linear ferroelectric layers 14 may be formed by patterningusing a mask used to pattern the second signal electrodes 16 asdescribed later.

[0070] A protective layer may optionally be formed of an insulatinglayer so as to cover the dielectric layers 18 and the second signalelectrodes 16.

[0071] (Operations of Ferroelectric Memory Device)

[0072] An example of a read or write operation of the ferroelectricmemory device 1000 is described below.

[0073] In the read operation, a read voltage “V₀” is applied to thecapacitor in the selected cell. This also serves as a write operation ofdata “0”. At this time, current flowing through the selected bit line ora potential when causing the bit line to be in a high impedance state isread by the sense amplifier. A specific voltage is applied to thecapacitors in the non-selected cells in order to prevent occurrence ofcrosstalk during the read operation.

[0074] In the write operation, a voltage “−V₀” is applied to thecapacitor in the selected cell in the case of writing data “1”. In thecase of writing data “0”, a voltage which does not cause polarizationinversion of the selected cell to occur is applied to the capacitor inthe selected cell, thereby holding the “0” state written during the readoperation. At this time, a specific voltage is applied to the capacitorsin the non-selected cells in order to prevent occurrence of crosstalkduring the write operation.

[0075] (Fabrication Method)

[0076] An example of a method of manufacturing the ferroelectric memorydevice 1000 is described below. FIGS. 5 and 6 are cross-sectional viewsschematically showing fabrication steps of the ferroelectric memorydevice 1000.

[0077] (1) First signal electrode

[0078] The first signal electrodes (lower electrodes) 12 arranged in aspecific pattern are formed on the base 10, as shown in FIG. 5. Thefirst signal electrodes 12 are formed by depositing an electrodematerial for forming the first signal electrodes 12 on the base 10 andpatterning the deposited electrode material, for example.

[0079] There are no specific limitations to the electrode materialinsofar as the material has a function of making up part of theferroelectric capacitors. In the case of using PZT as the material forforming the ferroelectric layers 14, platinum, iridium, compoundsthereof, or the like may be used as the electrode material for the firstsignal electrodes 12. As the material for the first signal electrodes12, Ir, IrO_(x), Pt, RuO_(x), SrRuO_(x), and LaSrCoO_(x) can be given.The first signal electrodes 12 may be either a single layer or amultilayer consisting of a plurality of layers.

[0080] As the deposition method of the electrode material, sputtering,vacuum deposition, CVD, or the like may be used. As the patterningmethod, lithographic technology may be used. As the method forselectively removing the deposited electrode material, an etchingprocess such as RIE, sputter etching, or plasma etching may be used.

[0081] As the formation method of the electrode material, a method usingundercoat layers, which is described in a second embodiment (see steps(1) and (2) in “Device fabrication method” in the second embodiment),may be used without patterning by etching.

[0082] (2) Deposition of ferroelectric layer

[0083] A continuous layer 140 consisting of a ferroelectric material(hereinafter called “ferroelectric layer 140”) is formed on the entiresurface of the base 10 on which the first signal electrodes 12 with aspecific pattern are formed, as shown in FIG. 5. As the formation methodof the ferroelectric layer 140, a spin coating process or a dippingprocess using a sol-gel material or an MOD (Metal Organic Decomposition)material, a sputtering process, an MOCVD (Metal Organic Chemical VaporDeposition) process, and a laser ablation process can be given.

[0084] The composition of the material for the ferroelectric layer maybe appropriately selected insofar as the material exhibitsferroelectricity and can be used as a capacitor insulating film. Asexamples of such ferroelectrics, PZT (PbZr_(z)Ti_(1−z)O₃) and SBT(SrBi₂Ta₂O₉) can be given. Materials in which a metal such as niobium,nickel, or magnesium is added to these materials may also be applied. Asspecific examples of ferroelectrics, lead titanate (PbTiO₃), leadzirconate titanate (Pb(Zr,Ti)O₃), lead zirconate (PbZrO₃), lanthanumlead titanate ((Pb,La),TiO₃), lanthanum lead zirconate titanate ((Pb,La)(Zr,Ti)O₃), lead magnesium niobate zirconium titanate (Pb(Zr,Ti)(Mg,Nb)O₃), and the like may be used.

[0085] As the materials for these ferroelectrics, in the case of PZT,Pb(C₂H₅)₄, (C₂H₅)₃PbOCH₂C(CH₃)₃, or Pb(C₁₁H₁₉O₂)₂ for Pb, Zr(n-OC₄H₉)₄,Zr(t-OC₄H₉)₄, Zr(C₁₁H₁₉O₂)₄, or Zr(C₁₁H₁₉O₂)₄ for Zr, and Ti(i-C₃H₇)₄for Ti may be used. In the case of STB, Sr(C₁₁H₁₀O₂)₂ for Sr, Bi(C₆H₅)₃for Bi, and Ta(OC₂H₅)₅ for Ta may be used.

[0086] (3) Second signal electrode

[0087] The second signal electrodes (upper electrodes) 16 with aspecific pattern are formed on the ferroelectric layer 140, as shown inFIG. 5. The second signal electrodes 16 are formed by depositing anelectrode material for the second signal electrodes 16 on theferroelectric layer 140 and patterning the deposited electrode material,for example. Specifically, resist layers 30 with a specific pattern areformed on the deposited electrode material layer. The electrode materiallayer is selectively etched using the resist layers 30 as masks, wherebythe second signal electrodes 16 are formed.

[0088] The material, deposition method, and patterning method usinglithography for the second signal electrodes 16 are the same as those ofthe formation steps of the first signal electrodes 12 described in theabove (1). Therefore, further description is omitted.

[0089] (4) Patterning of ferroelectric layer

[0090] The ferroelectric layers 14 are patterned by selectively removingthe ferroelectric layer 140 using the resist layers 30 as masks, asshown in FIGS. 5 and 6. As the method for selectively removing thedeposited ferroelectric material, an etching process such as RIE,sputter etching, or plasma etching may be used. The resist layers 30 areremoved by a conventional method such as dissolving or ashing.

[0091] (5) Dielectric layer

[0092] The dielectric layers 18 are formed between the laminatesconsisting of the ferroelectric layer 14 and the second signal electrode16, as shown in FIG. 4. As the formation method of the dielectric layers18, a vapor phase process such as CVD, in particular, MOCVD, or a liquidphase process such as a spin coating process or a dipping process may beused.

[0093] As the material for the dielectric layers 18, it is preferable touse a dielectric material having a dielectric constant lower than thatof the ferroelectric layers 14 which make up the ferroelectriccapacitors. In the case of using a PZT material for the ferroelectriclayers, an inorganic material such as SiO₂, Ta₂O₅, SrTiO₃, or MgO, or anorganic material such as a polyimide may be used as the material for thedielectric layers 18. In the case of using an SBT material for theferroelectric layers 14, an inorganic material such as SiO₂, Ta₂O₅,SrTiO₃, SrTa₂O₆, or SrSnO₃, or an organic material such as a polyimidemay be used as the material for the dielectric layers 18.

[0094] The memory cell array 100A is formed by these steps. According tothis fabrication method, since the ferroelectric layers 14 which make upthe ferroelectric capacitors 20 are continuously patterned using theresist layers 30 used to pattern the second signal electrodes 16 asmasks, the number of fabrication steps can be decreased. Moreover, sincethe alignment tolerance for one mask becomes unnecessary in comparisonwith the case of patterning each layer using different masks, the memorycell array can be highly integrated.

[0095] Second Embodiment

[0096]FIG. 7 is a plan view schematically showing a portion of a memorycell array including ferroelectric capacitors according to thisembodiment. FIG. 8 is a cross-sectional view along the line B-B shown inFIG. 7.

[0097] In this embodiment, components having substantially the samefunctions as those of the memory cell array of the first embodiment aredenoted by the same reference numerals.

[0098] This embodiment differs from the first embodiment in that theferroelectric layers which make up the ferroelectric capacitors arelinearly layered on the first signal electrodes (lower electrodes).

[0099] In a memory cell array 100B, the first signal electrodes 12, theferroelectric layers 14 which make up the ferroelectric capacitors, andthe second signal electrodes 16 are layered on the insulating base 10.The first signal electrode 12, the ferroelectric layer 14, and thesecond signal electrode 16 make up the ferroelectric capacitor 20.Specifically, memory cells consisting of the ferroelectric capacitors 20are formed in each intersection region between the first signalelectrodes 12 and the second signal electrodes 16.

[0100] The first signal electrodes 12 and the second signal electrodes16 are respectively arranged in the X direction and the Y direction at aspecific pitch, as shown in FIG. 7.

[0101] The ferroelectric layers 14 are selectively formed on the firstsignal electrodes 12. Undercoat layers 22 are formed on the base 10between the first signal electrodes 12. The dielectric layers 18 areformed on the undercoat layers 22. The dielectric layers 18 preferablyhave a dielectric constant lower than that of the ferroelectric layers14. The parasitic capacitance of the second signal electrodes 16 can bedecreased by allowing the dielectric layers 18 having a dielectricconstant lower than that of the ferroelectric layers 14 to be interposedbetween laminates consisting of the first signal electrode 12 and theferroelectric layer 14. As a result, a read or write operation of theferroelectric memory device can be performed at a higher speed.

[0102] (Fabrication Method)

[0103] FIGS. 9 to 12 are cross-sectional views schematically showingmanufacturing steps of the memory cell array 100B.

[0104] (1) Undercoat layer

[0105] A step of providing selectivity to the surface properties of thebase 10 is performed. Providing selectivity to the surface properties ofthe base 10 means defining regions having different surface properties,such as wettability for materials to be deposited, on the surface of thebase 10.

[0106] First regions 24 having an affinity for the materials formingcomponents of the ferroelectric capacitors, particularly for thematerials of the electrodes, and second regions 26 having a low affinityfor the materials forming the components of the ferroelectriccapacitors, particularly for the materials of the electrodes incomparison with the affinity of the first regions 24 are defined on thesurface of the base 10, as shown in FIG. 9. The ferroelectric capacitorsare selectively formed in the first regions 24 in the succeeding stepsby utilizing selectivity between each region relating to the depositionrate of the materials or adhesion to the base caused by the differencein the surface properties.

[0107] Specifically, at least either the first signal electrodes 12 orferroelectric layers 14 of the ferroelectric capacitors can be formed inthe first regions 24 in the succeeding steps by a selective depositionprocess using a chemical vapor deposition (CVD) process, a physicalvapor deposition process, or a liquid phase process, for example. In thecase where the surface of the base 10 has properties which cause thematerials for forming the components of the ferroelectric capacitors tobe easily deposited, the surface of the base may be exposed in the firstregions 24 and the undercoat layers 22 on which the above materials aredeposited to only a small extent may be formed in the second regions 26,thereby providing selectivity relating to deposition of the materialsfor forming the components of the ferroelectric capacitors.

[0108] In this embodiment, the undercoat layer is formed over the entiresurface of the base 10. The undercoat layer is removed in the firstregions 24 while allowing the undercoat layers 22 to remain in thesecond regions 26, as shown in FIG. 9. Specifically, the following stepsare performed.

[0109] The undercoat layers 22 may be formed using a vapor phasedeposition process such as CVD or using a liquid phase process such as aspin coating process or a dipping process. In the latter case, liquid ora substance dissolved in a solvent is used. A silane coupling agent(organosilicon compound) or a thiol compound may be used as such asubstance.

[0110] A thiol compound is a generic name for organic compoundscontaining a mercapto group (—SH) (R¹—SH; wherein R¹ represents areplaceable hydrocarbon group such as an alkyl group). Such a thiolcompound is dissolved in an organic solvent such as dichloromethane ortrichloromethane to prepare a solution at a concentration of about 0.1to 10 mM, for example.

[0111] A silane coupling agent is a compound shown by R² _(n)SiX_(4−n)(wherein n is a natural number, R² represents a hydrogen atom or areplaceable hydrocarbon group such as an alkyl group), wherein Xrepresents —OR³, —COOH, —OOCR³, —NH_(3−n)R³ _(n), —OCN, halogen, or thelike (wherein R³ represents a replaceable hydrocarbon group such as analkyl group). Of these silane coupling agents and thiol compounds,compounds containing a fluorine atom in which R¹ or R³ isC_(n)F_(2n+1)C_(m)H_(2m) (wherein n and m are natural numbers) areparticularly preferable, because surface free energy of these compoundsis increased and an affinity for other materials is lowered.

[0112] In addition, films obtained using a compound containing amercapto group or —COOH group by the above method may also be used.Films formed of these materials may be used in the form of amonomolecular film or a built-up film thereof using an appropriatemethod.

[0113] In this embodiment, the undercoat layer is not formed in thefirst regions 24, as shown in FIG. 9. In the case of using a silanecoupling agent for the undercoat layers 22, light irradiation may causethe molecular bonds to break at the interface with the base 10, wherebythe undercoat layer may be removed. Mask exposure performed inlithography may be applied to patterning using light. The undercoatlayers may be directly patterned using laser beams, electron beams, ionbeams, or the like without using a mask.

[0114] The undercoat layers 22 may be selectively formed in the secondregions 26 by transferring the undercoat layers 22 formed on anotherbase. This enables deposition and patterning to be performed at the sametime.

[0115] By causing the first regions 24 and the second regions 26 coveredwith the undercoat layers 22 to have different surface conditions, thedifference in affinity for the materials forming the components of theferroelectric capacitors in the succeeding steps can be produced, asshown in FIG. 9. In particular, if the undercoat layers 22 exhibit waterrepellency due to the possession of a fluorine molecule or the like, thematerial for forming the components of the ferroelectric capacitors canbe selectively provided at the first regions 24 by providing thematerial in a liquid phase. Depending on the material for the undercoatlayers 22, the material may be deposited in the first regions 24, onwhich the undercoat layers 22 are not present, using a vapor phaseprocess due to an affinity for the materials forming the upper layercomponents. The components (first signal electrodes 12 and ferroelectriclayers 14 in this embodiment) of the ferroelectric capacitors of theferroelectric memory device can be formed in the succeeding steps bythus providing selectivity to the surface properties of the firstregions 24 and the second regions 26.

[0116] (2) First signal electrode

[0117] The first signal electrodes 12 which become the lower electrodesof the ferroelectric capacitors are formed corresponding to the firstregions 24, as shown in FIG. 10. For example, a deposition step using avapor phase process is performed for the entire surface of the base 10.This allows the selective deposition process to be performed.Specifically, the material is deposited in the first regions 24, but isdeposited to only a small extent in the second regions 26, whereby thefirst signal electrodes 12 are formed only in the first regions 24. Itis preferable to apply CVD, in particular, MOCVD as the vapor phaseprocess. It is preferable that the material not be deposited in thesecond regions 26. However, it suffices that the deposition rate in thesecond regions 26 be two digits or more lower than that in the firstregions 24.

[0118] The first signal electrodes 12 may be formed using a method ofselectively supplying a solution of the material to the first regions 24in a liquid phase, or using a mist deposition process in which asolution of the material is misted using ultrasonic waves or the likeand selectively supplied to the first regions 24.

[0119] As the material for forming the first signal electrodes 12,platinum, iridium, or the like maybe used in the same manner as in thefirst embodiment. If the selectivity of surface properties is obtainedby forming the first regions 24 and the undercoat layers 22 (secondregions 26) containing the above material on the base 10, the materialfor forming the electrodes can be selectively deposited using(C₅H₇O₂)₂Pt, (C₅HFO₂)₂Pt, or (C₃H₅)(C₅H₅)Pt for platinum or (C₃H₅)₃Irfor iridium.

[0120] (3) Ferroelectric layer

[0121] The ferroelectric layers 14 are formed on the first signalelectrodes 12, as shown in FIG. 11. Specifically, a deposition stepusing a vapor phase process is performed for the entire surface of thebase 10, for example. The material is deposited on the first signalelectrodes 12, but is deposited to only a small extent in the secondregions 26, whereby the ferroelectric layers 14 are formed only on thefirst signal electrodes 12. As the vapor phase process, CVD, inparticular, MOCVD may be applied.

[0122] The ferroelectric layers 14 may be formed using a method ofselectively supplying a solution of the material to the first signalelectrodes 12 formed other than the second regions 26 in a liquid phaseusing an ink jet process or the like, or using a mist deposition processin which a solution of the material is misted using ultrasonic waves orthe like and selectively supplied to the regions other than secondregions 26.

[0123] The composition of the material for the ferroelectric layers 14may be appropriately selected insofar as the material exhibitsferroelectricity and can be used as a capacitor insulating film. Forexample, SBT materials, PZT materials, materials to which niobium or ametal oxide such as nickel oxide or magnesium oxide is added, or thelike may be used. As specific examples of ferroelectrics, theferroelectrics described in the first embodiment can be given. Asspecific examples of the materials for ferroelectrics, the materialsdescribed in the first embodiment can be given.

[0124] (4) Dielectric layer

[0125] The dielectric layers 18 are formed in the second regions 26,specifically, in the regions between laminates consisting of the firstsignal electrode 12 and the ferroelectric layer 14 formed in the firstregions 24, as shown in FIG. 12. As the formation method of thedielectric layers 18, a vapor phase process such as CVD, in particular,MOCVD, or a liquid phase process such as a spin coating process or adipping process may be used. The dielectric layers 18 are preferablyplanarized so as to have a surface at the same level as theferroelectric layers 14 using a CMP (Chemical Mechanical Polishing)process or the like. The second signal electrodes 16 can be easilyformed with high accuracy by planarizing the dielectric layers 18 inthis manner.

[0126] As the material for the dielectric layers 18, it is preferable touse a dielectric material having a dielectric constant lower than thatof the ferroelectric layers 14 which make up the ferroelectriccapacitors. In the case of using a PZT material for the ferroelectriclayers, an inorganic material such as SiO₂, Ta₂O₅, SrTiO₃, or MgO, or anorganic material such as a polyimide may be used as the material for thedielectric layers 18. In the case of using an SBT material for theferroelectric layers 14, an inorganic material such as SiO₂, Ta₂O₅,SrTiO₃, SrTa₂O₆, or SrSnO₃, or an organic material such as a polyimidemay be used as the material for the dielectric layers 18.

[0127] (5) Second signal electrode

[0128] The second signal electrodes (upper electrodes) 16 with aspecific pattern are formed on the ferroelectric layers 14 and thedielectric layers 18, as shown in FIG. 8. The second signal electrodes16 are formed by depositing an electrode material for the second signalelectrodes 16 on the ferroelectric layers 14 and the dielectric layers18 and patterning the deposited electrode material, for example.

[0129] There are no specific limitations to the electrode materialinsofar as the material has a function of making up part of theferroelectric capacitors. In the case of using PZT as the material forforming the ferroelectric layers 14, platinum, iridium, compoundsthereof, or the like may be used as the electrode material for thesecond signal electrodes 16, in the same manner as in the firstembodiment. The second signal electrodes 16 may be either as a singlelayer or a multilayer consisting of a plurality of layers.

[0130] As the deposition method of the electrode material, sputtering,vacuum deposition, CVD, or the like may be used in the same manner as inthe first embodiment. As the patterning method, lithographic technologymay be used.

[0131] An insulating protective layer may optionally be formed on theentire surfaces of the ferroelectric layers 14, dielectric layers 18,and second signal electrodes 16. The memory cell array 100B can beformed in this manner.

[0132] According to the fabrication method of this embodiment of thepresent invention, at least one component which makes up theferroelectric capacitor can be selectively formed in the first regions24, but is formed to only a small extent in the second regions 26.Therefore, at least either the first signal electrodes (lowerelectrodes) or ferroelectric layers (first signal electrodes 12 andferroelectric layers 14 in this embodiment) can be formed withoutetching. This method can prevent occurrence of a problem relating toreadhering substances caused by by-products produced during etching suchas in the case of patterning the first signal electrodes using sputteretching.

[0133] In the fabrication method of this embodiment, the undercoatlayers 22 maybe removed in the second regions 26 after the step shown inFIG. 11. This step is performed after the deposition steps of the firstsignal electrodes 12 and the ferroelectric layers 14 have beencompleted. The undercoat layers 22 may be removed using the methoddescribed relating to the patterning step of the undercoat layers, forexample. It is preferable to remove substances adhering to the undercoatlayers 22 when removing the undercoat layers 22. For example, in thecase where the material for the first signal electrodes 12 or theferroelectric layers 14 adheres to the undercoat layers 22, such amaterial may be removed. The step of removing the undercoat layers 22 isnot an indispensable condition for the present invention. The undercoatlayers 22 may be allowed to remain.

[0134] In the case where the ferroelectric layers 14 are formed on theside of the first signal electrodes 12, it is preferable to remove theseferroelectric layers. In the removal step, dry etching may be applied,for example.

[0135] In this embodiment, the undercoat layers 22 are formed in thesecond regions 26 so that the first regions 24 and the second regions 26have surface properties differing in deposition capability of thematerial for forming at least one component (at least either the firstsignal electrode or ferroelectric layer) of the ferroelectric capacitorsto be formed in the succeeding steps. As a modification example, theundercoat layers 22 may be formed in the first regions 24. Theferroelectric capacitors maybe selectively formed in the first regions24 by preparing the material for forming at least one component of theferroelectric capacitors so as to have a composition in a liquid phaseor a vapor phase so that the material is deposited preferentially on thesurface of the undercoat layers 22.

[0136] Thin undercoat layers may be selectively formed on the surface ofthe second regions 26. The material for forming at least one componentof the ferroelectric capacitors may be supplied in a vapor phase or in aliquid phase over the entire surface of the base including the firstregions 24 and the second regions 26, thereby forming the material layerfor this component on the entire surface. The material layer for thiscomponent may be selectively removed by polishing or by a chemicaltechnique only on the thin undercoat layers to selectively obtain thematerial layers for this component in the first regions 24.

[0137] In addition, a surface treatment may be selectively performedwithout forming layers on the surfaces of the first regions 24 and thesecond regions 26 so that the material for forming at least onecomponent of the ferroelectric capacitors is deposited preferentially inthe first regions 24.

[0138] Formation of the first signal electrodes (lower electrodes) andthe ferroelectric layers using the undercoat layers, which is thefeature of this embodiment of the present invention, is described in anInternational Patent Application based on the patent cooperation treatyapplied for by the applicant of the present invention (applicationnumber: PCT/JP00/03590).

[0139] Third Embodiment

[0140]FIG. 13 is a plan view schematically showing a portion of a memorycell array including ferroelectric capacitors according to thisembodiment of the present invention. FIG. 14 is a cross-sectional viewalong the line C-C shown in FIG. 13. FIG. 15 is a cross-sectional viewalong the line D1-D1 shown in FIG. 13. FIG. 16 is a cross-sectional viewalong the line D2-D2 shown in FIG. 13.

[0141] In this embodiment, sections having substantially the samefunctions as those of the memory cell array of the first embodiment areindicated by the same symbols.

[0142] This embodiment differs from the first and second embodiments inthat the ferroelectric layers which make up the ferroelectric capacitorsare formed only in the intersection regions between the first signalelectrodes and the second signal electrodes.

[0143] In a memory cell array 100C, the first signal electrodes 12, theferroelectric layers 14 which make up the ferroelectric capacitors, andthe second signal electrodes 16 are layered on the insulating base 10.The first signal electrode 12, the ferroelectric layer 14, and thesecond signal electrode 16 make up the ferroelectric capacitor 20.Specifically, memory cells consisting of the ferroelectric capacitors 20are formed in each intersection region between the first signalelectrodes 12 and the second signal electrodes 16. The first signalelectrodes 12 and the second signal electrodes 16 are respectivelyarranged in the X direction and the Y direction at a specific pitch, asshown in FIG. 13.

[0144] The ferroelectric layers 14 are selectively formed only in theintersection regions between the first signal electrodes 12 and thesecond signal electrodes 16. In a view along the second signal electrode16 shown in FIG. 14, the ferroelectric layers 14 and the second signalelectrodes 16 are layered on the first signal electrodes 12 on the base10. The undercoat layers 22 are disposed between the first signalelectrodes 12. The dielectric layers 18 are formed on the undercoatlayers 22. In a view along the first signal electrode 12 shown in FIG.15, the ferroelectric layers 14 and the second signal electrodes 16 arelayered at a specific position of the first signal electrodes 12. Nolayer is present between laminates consisting of the ferroelectric layer14 and the second signal electrode 16. In a view along the first signalelectrode 12 shown in FIG. 15, the ferroelectric layers 14 and thesecond signal electrodes 16 are layered at a specific position of thefirst signal electrodes 12. In a view along the X direction shown inFIG. 16 in which the first signal electrodes 12 are not formed, thedielectric layers 18 and the second signal electrodes 16 are layered ata specific position of the undercoat layer 22. Dielectric layers mayoptionally be formed between laminates consisting of the ferroelectriclayer 14 and the second signal electrode 16 and between laminatesconsisting of the dielectric layer 18 and the second signal electrode16.

[0145] The dielectric layers 18 and the dielectric layers which areoptionally formed preferably have a dielectric constant lower than thatof the ferroelectric layers 14. The parasitic capacitance of the firstsignal electrodes 12 and the second signal electrodes 16 can bedecreased by allowing the dielectric layers having a dielectric constantlower than that of the ferroelectric layers 14 to be interposed betweenthe laminates consisting of the first signal electrode 12 and theferroelectric layer 14 or between the laminates consisting of theferroelectric layer 14 and the second signal electrode 16. As a result,a read or write operation of the ferroelectric memory device can beperformed at a higher speed.

[0146] In this embodiment of the present invention, the ferroelectriclayers 14 which make up the ferroelectric capacitors 20 are formed onlyin the intersection regions between the first signal electrodes 12 andthe second signal electrodes 16. According to this configuration, theparasitic capacitance of both the first signal electrodes 12 and thesecond signal electrodes 16 can be decreased.

[0147] (Fabrication Method)

[0148] FIGS. 17 to 24 are cross-sectional views schematically showingmanufacturing steps of the memory cell array 100C according to thisembodiment of the present invention.

[0149] (1) Undercoat layer

[0150] A step of providing selectivity to the surface properties of thebase 10 is performed. Providing selectivity to the surface properties ofthe base 10 means defining regions having different surface propertiessuch as wettability for materials to be deposited on the surface of thebase 10. Since the details are described in the second embodiment, onlybrief description is given below.

[0151] In this embodiment, the first regions 24 having an affinity forthe materials forming the components of the ferroelectric capacitors,particularly for the materials of the electrodes, and the second regions26 having a low affinity for the materials forming the components of theferroelectric capacitors, particularly for the materials of theelectrodes in comparison with the first regions 24 are defined on asurface of the base 10, as shown in FIG. 9. The ferroelectric capacitorsare selectively formed in the first regions 24 in the succeeding stepsby utilizing selectivity between each region relating to the depositionrate of the materials or adhesion to the base caused by the differencein the surface properties.

[0152] Specifically, in the case where the surface of the base 10 hasproperties which cause the materials for forming the components of theferroelectric capacitors to be easily deposited, the surface of the basemay be exposed in the first regions 24 and the undercoat layers 22 onwhich the above materials are deposited to only a small extent may beformed in the second regions 26, thereby providing selectivity relatingto deposition of the materials for forming the components of theferroelectric capacitors.

[0153] In this embodiment, the undercoat layer is formed over the entiresurface of the base 10. The undercoat layer is removed in the firstregions 24 while allowing the undercoat layers 22 to remain in thesecond regions 26, as shown in FIG. 18. As the formation method of theundercoat layers 22, the method described in the second embodiment maybe employed.

[0154] (2) First signal electrode

[0155] The first signal electrodes 12 which become the lower electrodesof the ferroelectric capacitors are formed corresponding to the firstregions 24, as shown in FIG. 19. As the formation method and theelectrode material for the first signal electrodes 12, the method andthe material described in the second embodiment may be employed.

[0156] (3) Ferroelectric layer

[0157] Ferroelectric layers 140 are formed on the first signalelectrodes 12 as shown in FIG. 20. Specifically, a deposition step usinga vapor phase process is performed for the entire surface of the base10. This causes the material to be deposited on the first signalelectrodes 12, but to be deposited to only a small extent in the secondregions 26, whereby the ferroelectric layers 140 are formed only on thefirst signal electrodes 12. As the deposition method of theferroelectric layers 140, the method described in the second embodimentmay be employed.

[0158] The composition of the material for the ferroelectric layers 14may be appropriately selected insofar as the material exhibitsferroelectricity and can be used as a capacitor insulating film. Forexample, SBT materials, PZT materials, materials to which a metal suchas niobium, nickel, or magnesium is added, or the like may be used. Asspecific examples of ferroelectrics, the ferroelectrics described in thefirst embodiment can be given. As specific examples of the materials forferroelectrics, the materials described in the first embodiment can begiven.

[0159] (4) Dielectric layer

[0160] Dielectric layers 180 are formed in the second regions 26,specifically, in the regions between the laminates consisting of thefirst signal electrode 12 and the ferroelectric layer 14 formed in thefirst regions 24, as shown in FIGS. 17 and 21. FIG. 21 is across-sectional view along the line E-E shown in FIG. 17.

[0161] As the formation method of the dielectric layers 180, the methoddescribed in the first embodiment may be employed. The dielectric layers180 are preferably planarized using a CMP process or the like so as tohave a surface at the same level as the ferroelectric layers 140. Thesecond signal electrodes 16 can be easily formed with high accuracy byplanarizing the dielectric layers 180 in this manner.

[0162] As the material for the dielectric layers 180, it is preferableto use a dielectric material having a dielectric constant lower thanthat of the ferroelectric layers 14 which make up the ferroelectriccapacitors. In the case of using a PZT material for the ferroelectriclayers, an inorganic material such as SiO₂, Ta₂O₅, SrTiO₃, or MgO, or anorganic material such as a polyimide may be used as the material for thedielectric layers 180. In the case of using an SBT material for theferroelectric layers 14, an inorganic material such as SiO₂, Ta₂O₅,SrTiO₃, SrTa₂O₆, or SrSnO₃, or an organic material such as a polyimidemay be used as the material for the dielectric layers 180.

[0163] The first signal electrodes 12 and the ferroelectric layers 140are layered in the first regions 24, and the undercoat layers 22 and thedielectric layers 180 are layered in the second regions 26 by the steps(1) to (4).

[0164] (5) Second signal electrode

[0165] The second signal electrodes (upper electrodes) 16 with aspecific pattern are formed on the ferroelectric layers 140 and thedielectric layers 180, as shown in FIGS. 22 to 24. The second signalelectrodes 16 are formed by depositing an electrode material for formingthe second signal electrodes 16 on the ferroelectric layers 140 and thedielectric layers 180 and patterning the deposited electrode material,for example.

[0166] There are no specific limitations to the electrode materialinsofar as the material has a function of making up part of theferroelectric capacitors. As the material for forming the ferroelectriclayers 140, the material described in the first embodiment may beemployed. As the deposition method of the electrode material,sputtering, vacuum deposition, CVD, or the like may be used in the samemanner as in the first embodiment. As the patterning method,lithographic technology may be used.

[0167] For example, the second signal electrodes 16 may be patterned byforming resist layers (not shown) on the electrode material layer forthe second signal electrodes 16 and etching the electrode material layerusing the resist layers as masks, in the same manner as in the firstembodiment.

[0168] (6) Patterning of ferroelectric layer

[0169] The ferroelectric layers 14 are patterned by selectively removingthe ferroelectric layers 140 using the resist layers (not shown) asmasks, as shown in FIGS. 15 and 16. As the method for selectivelyremoving the deposited ferroelectric material, an etching process suchas RIE, sputter etching, or plasma etching may be used in the samemanner as in the first embodiment. The resist layers are removed by aconventional method such as dissolving or ashing.

[0170] (7) Further dielectric layer

[0171] If necessary, further dielectric layers (not shown) may be formedbetween the laminates consisting of the ferroelectric layer 14 and thesecond signal electrode 16 and between the laminates consisting of theundercoat layer 22 and the second signal electrode 16. As the formationmethod of the dielectric layers, the formation method of the dielectriclayers 180 in the step (4) may be used.

[0172] The memory cell array 100C is formed by these steps. Thisfabrication method has the same advantages as in the first embodimentand the second embodiment. Specifically, at least either the firstsignal electrodes (lower electrodes) or ferroelectric layers (firstsignal electrodes 12 and ferroelectric layers 14 of this embodiment) canbe formed without etching. Therefore, occurrence of a problem relatingto readhering substances caused by by-products produced during etchingsuch as in the case of patterning the first signal electrodes usingsputter etching can be prevented. Moreover, since the ferroelectriclayers 14 are patterned continuously using the resist layers used topattern the second signal electrodes 16 as masks, the number offabrication steps can be decreased. Furthermore, since the alignmenttolerance for one mask becomes unnecessary in comparison with the caseof patterning each layer using different masks, the memory cell arraycan be highly integrated.

[0173] The above examples illustrate cases in which the dielectriclayers 18 or 180 are formed in the regions in which the ferroelectriccapacitors are not present. However, the present invention can beapplied to configurations in which the dielectric layers 18 or 180 arenot provided.

What is claimed is:
 1. A memory cell array having ferroelectriccapacitors, wherein: memory cells formed of ferroelectric capacitors arearranged in a matrix; each of the ferroelectric capacitors includes afirst signal electrode, a second signal electrode disposed in adirection intersecting the first signal electrode, and a ferroelectriclayer disposed at least in an intersection area of the first and secondsignal electrodes; and the ferroelectric layer is disposed linearlyalong one of the first signal electrode and the second signal electrode.2. The memory cell array having ferroelectric capacitors as defined inclaim 1, wherein the ferroelectric layer is selectively disposed overthe first signal electrode.
 3. The memory cell array havingferroelectric capacitors as defined in claim 1, wherein theferroelectric layer is selectively disposed under the second signalelectrode.
 4. A memory cell array having ferroelectric capacitors,wherein: memory cells formed of ferroelectric capacitors are arranged ina matrix; each of the ferroelectric capacitors includes a first signalelectrode, a second signal electrode disposed in a directionintersecting the first signal electrode, and a ferroelectric layerdisposed at least in an intersection area of the first and second signalelectrodes; and the ferroelectric layer is disposed only in theintersection area of the first and second signal electrodes.
 5. Thememory cell array having ferroelectric capacitors as defined in claim 2,wherein: the ferroelectric capacitors are disposed on a base; and adielectric layer is provided between laminates each of which includesthe first signal electrode and the ferroelectric layer so as to cover anexposed surface of the base.
 6. The memory cell array havingferroelectric capacitors as defined in claim 5, wherein the dielectriclayer is formed of a material having a dielectric constant lower than adielectric constant of the ferroelectric layer.
 7. The memory cell arrayhaving ferroelectric capacitors as defined in claim 5, wherein anundercoat layer having surface properties differing from surfaceproperties of the base is formed on the base.
 8. The memory cell arrayhaving ferroelectric capacitors as defined in claim 7, wherein: theundercoat layer is provided in an area in which the ferroelectriccapacitors are not formed; and a surface of the undercoat layer has alow affinity for a material forming the ferroelectric capacitors, incomparison with a surface of the base.
 9. The memory cell array havingferroelectric capacitors as defined in claim 7, wherein: the undercoatlayer is provided in an area in which the ferroelectric capacitors areformed; and a surface of the undercoat layer has a high affinity for amaterial forming the ferroelectric capacitors, in comparison with asurface of the base.
 10. The memory cell array having ferroelectriccapacitors as defined in claim 3, wherein: the ferroelectric capacitorsare disposed on a base; and a dielectric layer is provided betweenlaminates each of which includes the second signal electrode and theferroelectric layer so as to cover an exposed surface of the base and anexposed surface of the first signal electrode.
 11. The memory cell arrayhaving ferroelectric capacitors as defined in claim 10, wherein thedielectric layer is formed of a material having a dielectric constantlower than a dielectric constant of the ferroelectric layer.
 12. Thememory cell array having ferroelectric capacitors as defined in claim 4,wherein: the ferroelectric capacitors are disposed on a base; and adielectric layer is provided between laminates each of which includesthe first signal electrode and the ferroelectric layer so as to coverpart of an exposed surface of the base.
 13. The memory cell array havingferroelectric capacitors as defined in claim 12, wherein the dielectriclayer covers the exposed surface of the base and an exposed surface ofthe first signal electrode.
 14. The memory cell array havingferroelectric capacitors as defined in claim 12, wherein the dielectriclayer is formed of a material having a dielectric constant lower than adielectric constant of the ferroelectric layer.
 15. The memory cellarray having ferroelectric capacitors as defined in claim 12, wherein anundercoat layer having surface properties differing from surfaceproperties of the base is formed on the base.
 16. The memory cell arrayhaving ferroelectric capacitors as defined in claim 15, wherein: theundercoat layer is provided in an area in which the ferroelectriccapacitors are not formed; and a surface of the undercoat layer has alow affinity for a material forming the ferroelectric capacitors, incomparison with a surface of the base.
 17. The memory cell array havingferroelectric capacitors as defined in claim 15, wherein: the undercoatlayer is provided in an area in which the ferroelectric capacitors areformed; and a surface of the undercoat layer has a high affinity for amaterial forming the ferroelectric capacitors, in comparison with asurface of the base.
 18. A method of fabricating a memory cell array inwhich memory cells formed of ferroelectric capacitors are arranged in amatrix, comprising the steps of: forming a first signal electrode with apredetermined pattern on a base; selectively forming a ferroelectriclayer on the first signal electrode linearly along the first signalelectrode; and forming a second signal electrode in a directionintersecting the first signal electrode.
 19. The method of fabricating amemory cell array as defined in claim 18, further comprising the stepsof: forming on the base a first region having surface properties whichgive priority in deposition to a material of at least one of the firstsignal electrode and the ferroelectric layer, and a second region havingsurface properties which give difficulty in deposition to the materialof at least one of the first signal electrode and the ferroelectriclayer in comparison with the first region; and providing the material ofat least one of the first signal electrode and the ferroelectric layerand selectively forming one of the first signal electrode and theferroelectric layer in the first region.
 20. The method of fabricating amemory cell array as defined in claim 19, wherein the first and secondregions are defined on a surface of the base.
 21. The method offabricating a memory cell array as defined in claim 20, wherein: thesurface of the base is exposed in the first region; and in the secondregion is formed an undercoat layer having surface properties having alow affinity for materials of the first signal electrode and theferroelectric layer in comparison with the exposed surface of the basein the first region.
 22. The method of fabricating a memory cell arrayas defined in claim 20, wherein: the surface of the base is exposed inthe second region; and in the first region is formed an undercoat layerhaving surface properties having a high affinity for materials of thefirst signal electrode and the ferroelectric layer in comparison withthe exposed surface of the base in the second region.
 23. The method offabricating a memory cell array as defined in claim 18, wherein adielectric layer is provided between laminates each of which includesthe first signal electrode and the ferroelectric layer so as to cover anexposed surface of the base.
 24. The method of fabricating a memory cellarray as defined in claim 23, wherein the dielectric layer is formed ofa material having a dielectric constant lower than a dielectric constantof the ferroelectric layer.
 25. A method of fabricating a memory cellarray in which memory cells formed of ferroelectric capacitors arearranged in a matrix, comprising the steps of: forming a first signalelectrode with a predetermined pattern on a base; and forming aferroelectric layer and a second signal electrode in a directionintersecting the first signal electrode, wherein the ferroelectric layeris disposed linearly along the second signal electrode.
 26. The methodof fabricating a memory cell array as defined in claim 25, wherein theferroelectric layer and the second signal electrode are patterned byetching using the same mask.
 27. The method of fabricating a memory cellarray as defined in claim 25, wherein a dielectric layer is providedbetween laminates each of which includes the second signal electrode andthe ferroelectric layer so as to cover an exposed surface of the baseand an exposed surface of the first signal electrode.
 28. The method offabricating a memory cell array as defined in claim 27, wherein thedielectric layer is formed of a material having a dielectric constantlower than a dielectric constant of the ferroelectric layer.
 29. Amethod of fabricating a memory cell array in which memory cells formedof ferroelectric capacitors are arranged in a matrix, comprising thesteps of: forming a first signal electrode with a predetermined patternon a base; forming a ferroelectric layer on the first signal electrodelinearly along the first signal electrode; forming a second signalelectrode in a direction intersecting the first signal electrode; andpatterning the ferroelectric layer to be disposed only in anintersection area of the first and second signal electrodes.
 30. Themethod of fabricating a memory cell array as defined in claim 29,further comprising the steps of: forming on the base a first regionhaving surface properties which give priority in deposition to amaterial of at least one of the first signal electrode and theferroelectric layer, and a second region having surface properties whichgive difficulty in deposition to the material of at least one of thefirst signal electrode and the ferroelectric layer in comparison withthe first region; and providing the material of at least one of thefirst signal electrode and the ferroelectric layer and selectivelyforming one of the first signal electrode and the ferroelectric layer inthe first region.
 31. The method of fabricating a memory cell array asdefined in claim 30, wherein the first and second regions are formed ona surface of the base.
 32. The method of fabricating a memory cell arrayas defined in claim 31, wherein: part of the surface of the base isexposed in the first region; and in the second region is formed anundercoat layer having surface properties having a low affinity formaterials of the first signal electrode and the ferroelectric layer incomparison with the exposed surface of the base in the first region. 33.The method of fabricating a memory cell array as defined in claim 31,wherein: part of the surface of the base is exposed in the secondregion; and in the first region is formed an undercoat layer havingsurface properties having a high affinity for materials of the firstsignal electrode and the ferroelectric layer in comparison with theexposed surface of the base in the second region.
 34. The method offabricating a memory cell array as defined in claim 29, wherein theferroelectric layer and the second signal electrode are patterned byetching using the same mask.
 35. The method of fabricating a memory cellarray as defined in claim 29, wherein a dielectric layer is providedbetween laminates each of which includes the first signal electrode andthe ferroelectric layer so as to cover an exposed surface of the base.36. The method of fabricating a memory cell array as defined in claim35, wherein the dielectric layer is provided between laminates each ofwhich includes the second signal electrode and the ferroelectric layerso as to cover the exposed surface of the base and an exposed surface ofthe first signal electrode.
 37. The method of fabricating a memory cellarray as defined in claim 35, wherein the dielectric layer is formed ofa material having a dielectric constant lower than a dielectric constantof the ferroelectric layer.
 38. A ferroelectric memory device comprisingthe memory cell array as defined in any one of claims 1 to 17.